Title: EE4218_EHSD / Synthesis
On every note of this deck, unless a note says otherwise:
Title: EE4218_EHSD::Synthesis
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Front: What is a Logic Network?
Back: - An interconnection of blocks
- Each block modeled by a Boolean function

Front: What does a Vertex describe in a Logic Network?
Back: A multi-input/single-output leaf module

Front: How is this Diagram called?
Back: A Logic Network

Front: How is this Graph called?
Back: A Logic Network Graph

Front: What is a Dataflow Graph, and how is it used?
Back: A Graph with vertices = operations, and edges = dependencies.
Useful to represent data-paths.

Front: What is a Sequencing Graph, and how is it used?
Back: Extended dataflow graph with:
- Control-flow commands (Subroutines, Looping, and Branching)
- Source and Sink

Front: Give examples for vertex attributes in sequencing graphs.
Back: - Area cost
- Delay cost

Front: What are some estimates that can be made from a sequencing graph?
Back: - Area (worst-case): Sum of the area attributes of all vertices
- Delay Best-case (assuming no sharing): Length of longest path from source to sink assuming bounded latency

Front: What are the primary steps in behavioural synthesis?
Back: - Translate high-level models into sequencing graphs
- Behavioural-level optimisation
- Architectual synthesis and optimisation

Front: What is behavioural-level optimisation?
Back: Optimise abstract models independently from the implementation parameters

Front: How does hardware compilation work?
Back: - Compile high-level model into sequencing graph
- Optimise sequencing graph
- Generate gate-level interconnection for a cell library

Front: What is happening in the Compilation Front-end?
Back: - Lexer (Tokenisation)
- Parser (Syntax-Tree)
- Semantic Analysis

Front: What is Semantic Analysis in Hardware Compilation?
Back: - Data-flow and Control-flow analysis
- Type checking

Front: On what data structure do behavioural-level optimisations operate?
Back: Parse-trees

Front: What is Tree-height reduction?
Back: Reduce height of expression tree to exploit hardware parallelism

Front: What is operator-strength reduction?
Back: Reduce operator-strength, i.e. x**2 -> x * x

Front: What is architectural synthesis?
Back: Implementation of the design from optimized CDFGs (Control and Data Flow Graphs)

Front: What inputs are give for architectural synthesis?
Back: - Circuit behaviour (sequencing graph)
- Building blocks
- Constraints (e.g. timing, area, and resource)

Front: What is the main problem in architectural synthesis?
Back: Explore area/performance trade-off; determine an optimal implementation

Front: What is scheduling?
Back: Placing operand-operations in time. Schedules at which clock cycle it starts.

Front: What is binding?
Back: Placing operand-operations in time. Binds operation to instance of functional unit.

Front: What are some datapath building blocks?
Back: - Functional resources (ALU)
- Storage (memory and registers)
- Interfaces (buses and ports)
- Steering logic (multiplexers)

Front: What are some control unit building blocks?
Back: - State machine
- Microprogrammed

Front: What is a recource-dominated circuit?
Back: Area and performance depend on few, well-characterized fucntional resources (e.g. DSPs)

Front: What is a non resource-dominated circuit?
Back: Area and performance are strongly influenced by sparse logic, control, and wiring

Front: What does scheduling determine?
Back: latency and parallelism

Front: What is a scheduled sequencing graph?
Back: Sequencing graph with start-time annotation.

Front: What was the goal in this schedule?
Back: Minimize delay with unconstrained resource usage.

Front: What was the goal in this schedule?
Back: Constrained to use 1 resource for each type.

Front: What is Scheduling with Chaining?
Back: Operations that take less time combined into one cycle.

Front: What is binding?
Back: - Associating a resource with each operation with the same type
- Determines the area of the implementation

Front: What is sharing in binding?
Back: - Binding a resource to more than one operation
- Operations must not execute concurrently

Front: What is a bound sequencing graph?
Back: Sequencing graph with resource annotation.

Front: What was the binding strategy here?
Back: Dedicated binding, no resource sharing

Front: What was the binding strategy here?
Back: Resource sharing:
- 4 multipliers
- 2 ALUs

Front: How is Area estimated in resource-dominated circuits?
Back: Sum of the areas of the resources bound to the operations (determined by binding)

Front: How is Latency estimated in resource-dominated circuits?
Back: time(sink) - time(start) (determined by scheduling)

Front: How is Area estimated in non resource-dominated circuits?
Back: - Number of Registers, Muxes, and other components such as bus drivers
- statistical placement and wiring models
- Memory

Front: How is Latency estimated in non resource-dominated circuits?
Back: - Propagation delay of components
- Interconnect length

Front: What is a Design Space?
Back: Set of all feasible implementations

Front: What are some Implementation parameters that can be tracked in Design Space Exploitation?
Back: - Area
- Performance
  - Cycle-time
  - Latency
  - Throughut
- Power consumption

Front: What is Pareto optimal?
Back: State at which resources in a given system are optimized in a way that one dimension cannot improve without a second worsening.

Front: What is Horizontal Microcode?
Back: - One activation signal per resource
- Vector of activation signals is one microword

Front: Given 4 words of 11-bits of microcode, what's the width of the counter driving the ROM?
Back: log2(4) = 2 bit

Front: How is the following Microcode Architecture called?
Back: Horizontal Microcode

Front: How is the following Microcode Architecture called?
Back: Vertical Microcode

Front: What is the primary difference between horizontal and vertical microcode?
Back: The vertical microcode
- needs decoders at ROM output to decode activation signals
- can activate only one resource at a time

Front: What's the width of one microword in Vertical Microcode?
Back: [$]\log_2(n_{\text{act}}\text{bits})[/$] for [$]n_{\text{act}}[/$] activation signals

Front: What is Vertical Microcode with Grouping?
Back: Group operations into sets, and assign an encoding for each set. The microcode format is just a concatenation of the fields.

Front: How is the following Microcode Architecture called?
Back: Vertical Microcode with Grouping