Title: EE4218_EHSD / Verilog for Synthesis

Front: Why is the following circuit in general not synthesizable?
Back: regs and wires should not have multiple drivers
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Where should a wire appear in an assign statement?
Back: On the left-hand side.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Where should a reg appear in an always block?
Back: On the left-hand-side.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Is it allowed to assign the same wire multiple times?
Back: Not in general.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Is it ok to have a reg at the LHS of multiple statements within the same always block?
Back: Yes as long as the same type of assignment is used.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: What to consider when writing always blocks?
Back: Every always should follow one of the three templates given in the lecture.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Describe the purely combinational always block template.
Back: - All outputs of the block are SOP and POS functions of the current inputs of the block
- Every input must be present in the sensitivity list
- Use only blocking assignments (one can use non-blocking assignments for the outputs)
Regs
- must be assigned a meaningful value for every possible combination of inputs (i.e., all branches of if / case statements)
- reg appearing on both LHS and RHS within an always block should appear on the LHS before RHS.
- reg assigned using non-blocking assignment should not appear on the RHS of the same block
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Describe the synchronous always block template.
Back: - Only posedge/negedge CLK in the sensitivity list
- Only regs that change on the same edge of the same clock should be assigned in the always block
- Use non-blocking assignments for the outputs of the always block (signals)
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Why is it discouraged to use a synchronous always block with asynchronous reset?
Back: An asynchronous reset can cause metastability in a digital circuit because if the reset signal changes state near a clock edge, the circuit may enter an indeterminate state.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Is the following always block considered good practise?
always @ (posedge CLK or posedge RST) begin
  if(RST)
    Z <= 1'b0;
    //do not have anything else here
  else begin
    //the rest of the code goes here
    Z <= X | Y;
  end
end
Back: No! Synchronous always blocks with asynch set/reset can lead to metastability issues.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Physical registers are inferred when...
Back: - Non-blocking assignments of regs in synchronous always block
- Blocking assignment of regs in the synchronous part of an always block where they are read (on RHS) before being written (on LHS)
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Is it recommended to infer regs by reading from a reg, before being written?
Back: No.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Describe the 8 verilog coding guidelines
Back: 1. When modeling sequential logic, use nonblocking assignments.
2. When modeling latches, use nonblocking assignments.
3. When modeling combinational logic with an always block, use blocking assignments.
4. When modeling both sequential and combinational logic within the same always block, use nonblocking assignments.
5. Do not mix blocking and nonblocking assignments in the same always block.
6. Do not make assignments to the same variable from more than one always block.
7. Use $strobe to display values that have been assigned using nonblocking assignments.
8. Do not make assignments using #0 delays.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: When modeling sequential logic, use _____________ assignments.
Back: When modeling sequential logic, use nonblocking assignments.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: When modeling latches logic, use _____________ assignments.
Back: When modeling latches logic, use nonblocking assignments.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: When modeling combinational logic with an always block, use _____________ assignments.
Back: When modeling combinational logic with an always block, use blocking assignments.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: When modeling both sequential and combinational logic within the same always block, use ____________ assignments.
Back: When modeling both sequential and combinational logic within the same always block, use nonblocking assignments.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Do not mix blocking and nonblocking assignments in _______ always block.
Back: Do not mix blocking and nonblocking assignments in the same always block.
Title: EE4218_EHSD::Verilog for Synthesis
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Front: Do not make assignments to ________ variable from more than ___ always block.
Back: Do not make assignments to the same variable from more than one always block.
Title: EE4218_EHSD::Verilog for Synthesis
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