Title: EE4218_EHSD / Introduction
On every note of this deck, unless a note says otherwise:
Title: EE4218_EHSD::Introduction
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Front: What are characteristics of an embedded system?
Back: - Embedded into a larger system, doing a dedicated task
- Typically real-time
- Power, cost, size constraints

Front: What is an ASSP?
Back: A Application Specific Standard Product: An IC creasted and optimised for market and sold to multiple companies.

Front: What is an ASIC?
Back: Special-purpose device designed and/or used by a single company in a specific system.

Front: What is CMOS VLSI?
Back: Complementary metal oxide semiconductor (CMOS): Combination of N-channel MOS (NMOS) and P-channel MOS (PMOS) field effect transistors (FETs).

Front: What is a BJT?
Back: Bipolar Junction Transistor

Front: What are the levels of abstraction in digital circuit design?
Back: 1. Algorithm / System Level (untimed)
2. Register Transfer Level (RTL, timed)
3. Gate Level
4. Circuit Level
5. Layout Level

Front: Primary features between HDLs and traditional programming languages?
Back: - Event-based
- Allow real concurrency, timing, delays
- Coding and testing in the same language

Front: Describe the simplified FPGA / ASIC design flow!
Back: Functional Specification -> Behavioural Modeling -> Architectual Synthesis -> Logic Synthesis -> Physical Design

Front: What is the difference between a FPGA and ASIC design flow?
Back: - FPGA: physical design is converted into a bitstream for FPGA Programming.
- ASIC: Layout for fabrication

Front: What are Technology Libraries?
Back: - For ASICs
  - Gates or gate combinations
  - Characterized carefully by the foundry
- For FPGAs
  - Composed of functions offered by configurable logic blocks (CLBs)

Front: What is done in the Architectual Synthesis step?
Back: Convert purely functional/behavioural/algorithmic model into macroscopic structural model

Front: What is the result of Architectual Synthesis?
Back: Results in macroscopic-block-level cycle accurate functional specification

Front: What is Scheduling in Architectual Synthesis?
Back: Specifies which clock cycle an operand-operation is performed at

Front: What is Binding in Architectual Synthesis?
Back: Which specific macroscopic block (ALU, etc.) performs the operation

Front: What are the main steps in Logic Synthesis?
Back: 1. Logic optimisation
2. Technology mapping (library binding)

Front: What does RTL describe?
Back: The flow of signals between registers

Front: Registers can be described as a _____ ____.
Back: Registers can be described as a brick wall.

Front: What do RTL (logic) synthesis tools optimise?
Back: The combinational logic between the registers.

Front: What is the Critical Path?
Back: The Cominbational Path with the maximum delay.

Front: What is Placement in Physical Design?
Back: Shape of a cell to physical place in the layout

Front: What is Routing in Physical Design?
Back: Mapping of logical connections between cells to physical interconnects

Front: Describe the architecture of an FPGA!
Back: - Matrix of configurable logic blocks (CLBs) connected via programmable interconnects (switches)

Front: What parts other than CLBs do FPGAs usually have?
Back: - Blocks of high-speed static/dynamic RAMs
- Sometimes additional embedded processors, ALUs, etc.

Front: What are some advantages of FPGAs?
Back: - Scalable
- Fast deployable
- Bug fixes

Front: What are some disadvantages of FPGAs?
Back: - Power: 14 times ASIC's power
- Area/Cost: 35 times large than ASIC
- Speed: 3-4 times slower than ASIC