Title: EE4218_EHSD / Timing Analysis

Front: What is the Clk to output [$]Q[/$] propagation delay ([$]t_{CQ}[/$])?
Back: The time for output to change, following the launching clock edge. -> Propagation delay of the launching FF
Title: EE4218_EHSD::Timing Analysis
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Front: What is the setup time ([$]t_\text{setup}[/$])?
Back: The time for which the data (D) has to be stable before the capture clock edge to ensure reliable capture of data.
Title: EE4218_EHSD::Timing Analysis
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Front: What is the hold time ([$]t_\text{hold}[/$])?
Back: The time for which the data (D) has to be stable after the capture clock edge to ensure reliable capture of data.
Title: EE4218_EHSD::Timing Analysis
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Front: What happens if there is a change in D during aperture time Aperature time = setup time + hold time?
Back: FF might go into metastability.
Title: EE4218_EHSD::Timing Analysis
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Front: What is clock skew ([$]\delta\text{skew}[/$])
Back: Additional time required for the clock to reach the capture FF relative to the launching FF.
- Positive skew: Clock reaches the capture FF later than the launching FF
Title: EE4218_EHSD::Timing Analysis
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Front: What is the arrival time [$]\text{arrival time} = t_{CQ} + t_\text{logic_max}[/$]?
Back: Time at which D stabilizes with refrence to the launching edge.
Title: EE4218_EHSD::Timing Analysis
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Front: What is the required time [$]\text{required time} = T + \delta_\text{skew} - t_\text{setup}[/$]?
Back: Latest time the data needs to stabilize for reliable capture with reference to the launching edge.
Title: EE4218_EHSD::Timing Analysis
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Front: How is setup slack computed?
Back: Difference between the required time and the arrival time.
Title: EE4218_EHSD::Timing Analysis
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Front: Why should the data not arrive too fast?
Back: The arrival should be after the hold time of the capture FF has passed (arrival time > required time).
Title: EE4218_EHSD::Timing Analysis
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Q: Positive clock skews are good for [...]
A: fixing setup violations
Title: EE4218_EHSD::Timing Analysis

Q: Negative clock skew can guard against [...], but can cause {{c1:setup violation}}
A: hold violation
Title: EE4218_EHSD::Timing Analysis

Q: A circuit with setup violation can work at a [...].
A: lower frequency
Title: EE4218_EHSD::Timing Analysis

Q: A circuit with hold violation will [...].
A: not work at all
Title: EE4218_EHSD::Timing Analysis

Front: How are constraints provided for the synthesis tool?
Back: .xdc or .sdc file
Title: EE4218_EHSD::Timing Analysis
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Front: What is the create_clock function?
Back: Tells the tool the clock frequency we are targeting
Title: EE4218_EHSD::Timing Analysis
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Front: Explain the following command:
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
Back: - Create clock named sys_clk_pin
- 10ns period
- 50% duty cycle: 0 is the low time, and 5 the high time.
- clock signal is expected to come from clk port
Title: EE4218_EHSD::Timing Analysis
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Front: Explain the following command:
set_false_path -through [get_pins mux1/I0] -through [get_pins mux2/I0]
Back: Specifies paths not considered for timing analysis.
- -through [get_pins mux1/I0]: Applies the constraint to signals passing through pin I0 of instance mux1.
- -through [get_pins mux2/I0]: Further extends the false path to signals that also pass through pin I0 of instance mux2.
Title: EE4218_EHSD::Timing Analysis
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Front: What does set_multicycle_path do?
Back: - Used for combinational operations which require more than 1 cycle
Title: EE4218_EHSD::Timing Analysis
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Front: What does set_input_delay and set_output_delay do?
Back: Used to set combinational delays for inputs and outputs
Title: EE4218_EHSD::Timing Analysis
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