Title: EE4218_EHSD / High-Level Synthesis

Front: What are the HLS design steps?
Back: - Design entry
- C simulation
- C synthesis
- Hardware-Software Cosimulation
- Hardware export to logic synthesis tool
Title: EE4218_EHSD::High-Level Synthesis
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Front: How does HLS roughly work?
Back: ^¥ 1. Translate high-level code into sequencing graphs 2. Behavioural-level optimisation 3. Architectual synthesis and optimisation
Title: EE4218_EHSD::High-Level Synthesis
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Front: What are disadvantages of HLS?
Back: - Slight changes in code might have an avalanche effect
- Does not work well for control-oriented blocks
- Directives (e.g. #pragma) may be required
Title: EE4218_EHSD::High-Level Synthesis
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